1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which includes a word line driving circuit of the divisional decoding type.
2. Description of the Prior Art
The degree of integration of semiconductor memory devices increases with advances in the technology in fine working technique. In particular, high integration has been achieved with dynamic random access memories (hereinafter referred to as DRAMs) which have a simple memory structure, and at present, DRAMs of 16 Mbits are being mass-produced and sample shipment of DRAMs of 64 Mbits is also planned.
64-Mbit DRAMs are semiconductor memory devices of the divisional decoding type wherein word lines are divided into a plurality of blocks and a word line driving circuit for supplying current is provided for each block of word lines to achieve high speed driving of the word lines.
FIG. 1 is a circuit diagram showing the basic construction of a semiconductor memory device of the divisional decoding type, and FIG. 2 is a circuit diagram of a word line driving circuit represented by WD1a in FIG. 1.
A memory cell array is divided into a plurality of blocks each selected by an upper row address, and each block is divided into a plurality of sub blocks SB1a to SB1c, SB2a to SB2c and SB3a to SB3a in the word line direction.
Word line driving circuits WD1a to WD1d are disposed in a manner such that sub block SB1a, SB1b, SB1c line between word line driving circuit W1a and WD1b, WD1b and WD1c, WD1c, and WD1d, resectively. Word line driving circuits WD2a to WD2a, WD3a to WD3d and WD4a to WD4d are disposed with respect to sub block SB2a to SB2c, SB3a to SB3a and SB4a to SB4a in the same way as word line driving circuits WD1a to WD1d. Word lines in sub block SB1a are alternately connected with word line driving circuit WD1a and WD1b. Similarly, word lines in sublock SB1b, SB1c, . . . , SB4a are alternately connected with word line driving circuit WD1b and WD1c, WD1c, and WD1d, . . . , WD4c and WD4d, respectively.
Further, sensing amplifiers SA1a to SA1c, SA2a to SA2c, SA3a to SA3c and SA4a to SA4c for amplifying data of bit lines are provided for sub blocks SB1a to SB1c, SB2a to SB2c, SB3a to SB3a and SB4a to SB4a, respectively. Sensing amplifiers SA1a to SA1c, SA2a to SA2c, SA3a to SA3c and SA4a to SA4c are determined by upper row address signals S1 and S2 and are selectively activated by block select signals BLS1 to BLS4 outputted from block select signal generation circuit BSG1.
Memory cells MC0 and MC1 are disposed at points at which word lines WL0a and WL1a intersect with bit lines BL00 and BL10, respectively.
In order to select word line driving circuits WD1a to WD1d, complementary signals XSW and XSWB are outputted from row decoder RD1 to word line driving circuits WD1a to WD1d. Meanwhile, word line driving current supplying signals RA01 and RA11 supplied from word line driving current supplying circuit RAG run vertically with respect to word lines WL0a and WL1a on word lines WD1a to WD4d, and word line driving current supplying signal RA01 is inputted to word line driving circuits WD1a, WD2a, WD3a, WD4a, WD1c, WD2c, WD3c, WD4c while word line driving current supplying signal RA11 is inputted to word line driving circuits WD1b, WD2b, WD3b, WD4b, WD1d, WD2a, WD3d and WD4d. Row decoders RD2, RD3 and RD4 are provided corresponding to word line driving circuits WD2a to WD2a, WD3a to WD3d and WD4a to WD4d , respectively.
It is to be noted that, while, in the drawings, almost all of output signals of the row decoders, word lines, bit lines, memory cells and so forth are omitted for simplification of the drawings, each block has a similar construction.
Word line driving circuits WD1a to WD1d, WD2a to WD2a, WD3a to WD3d and WD4a to WD4d are each constituted from a driving circuit of the self-booting type as shown in FIG. 2.
If it is assumed that complementary signal XSW and word line driving current supplying signal RA01 are selected by a row address, then N-type transistor Q3 is put into an off-state by complementary signal XSWB. Consequently, the potential at node 1 rises from the ground potential to a potential equal to the difference between the power source voltage and the threshold level voltage of N-type transistor Q2. Then, when the potential of word line driving current supplying signal RA01 rises, the potential at node 1 rises due to self booting of the transistor to a potential higher than word line driving current supplying signal RA01, and the potential at word line WL0a rises to a potential equal to the potential of word line driving current supplying signal RA01. In this instance, not only in word line driving circuit WD1a but also in word line driving circuit WD1c, the potentials at word lines WL0b and WL0c rise so that memory cell on the word line as represented by MC0 is selected. Data of the selected memory cell is outputted to the bit line represented by BL00, and sensing amplifiers SA1 a to SA1c are activated by block select signal BLS1 to amplify the data.
With the circuit construction described above, the wiring line distance per word line is decreased, and the rising rate of the word lines can be increased.
The above-described circuit construction, however, has the following disadvantages:
Generally, the word line rising time depends upon the wiring line resistance and the load capacitance of the word line and the wiring line resistance and the load capacitance of the word line driving current supplying circuit. In particular, if the wiring line resistance and the load capacities of the word line and the word line driving current supplying circuit are increased, then the word line rising time lengthens. On the other hand, the current consumed in driving the word line increases in proportion to the sum of the load capacitance of the word line and the word line driving current supplying signal. However, the wiring line resistance and the load capacitance of the word line depends upon such parameters as the material forming the word line and the number of memory cells connected to the word line, and in addition, the number of word lines to be activated at a time depends upon factors such as the limitation of the refresh cycle. Accordingly, it is difficult to reduce the wiring line resistance and the load capacitance of the word line. On the other hand, with regard to the word line driving current supplying signal, the load capacitance is the sum of the wiring line capacitance and the diffused layer junction capacitance of the word line driving circuit to which the word line driving current supplying signal is inputted. While the wiring line capacitance depends upon the width, the thickness, and the length of the wiring line, width and the thickness cannot be greatly decreased because so doing would increase the resistance value. On the other hand, the wiring line cannot be shortened because of restrictions in terms of layout. Accordingly, in order to reduce the load capacitance of the word line driving current supplying signal, the diffused layer capacitance of the word line driving circuit should be decreased, that is, the number of word line driving circuits to be connected to one word line driving current supplying signal should be decreased.
In the conventional word line driving system based on the divisional decoding system described above, however, since a word line driving current supplying signal is inputted in common to word line driving circuits in a block selected by an upper row address, when the number of blocks increases as the storage capacity increases, or when the number of word lines per one block increases, the load capacitance of the word line driving current supplying signal also increases, possibly resulting in a drop in speed when driving word lines or in an increase of current consumption.